Eur. Phys. J. B 42, 113-117 (2004)
https://doi.org/10.1140/epjb/e2004-00362-y

An analytical study of substrate current in submicron MOS devices

¹ No. 66/3, ASIC, Texas Instruments, Bagmane Tech Park, C.V. Raman Nagar Post, Byrasandra, Bangalore, 560093 Karnataka, India
² Birla Institute of Technology and Science, Pilani, 333031 Rajasthan, India

Corresponding author: ^a gokul_vaidyanaath@yahoo.co.in

Received: 23 April 2004
Revised: 27 September 2004
Published online: 26 November 2004

Abstract

In the present communication we have tried to study the substrate current behavior in the sub-micron devices after solving the second order differential equation using appropriate boundary conditions. Simple and accurate models for maximum lateral field, drain saturation voltage and for ionization length have been developed. The simulation result of ionization length shows a good match with the known result. Analysis also shows that dominant contributor to the error in the ionization length is not only because of the excess saturated voltage but also due to the channel length and the gate to source voltage. For sub-micron devices the saturation region shifts towards the source for higher drain voltage and larger gate oxide thickness.